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AMIS-30512 Micro-Stepping Motor Driver
Introduction
The AMIS-30512 is a micro-stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply peripheral devices. The AMIS-30512 contains a current-translation table and takes the next micro-step depending on the clock signal on the "NXT" input pin and the status of the "DIR" (=direction) register or input pin. The chip provides a so-called "speed and load angle" output. This allows the creation of stall detection algorithms and control loops based on load-angle to adjust torque and speed. It is using a proprietary PWM algorithm for reliable current control. The AMIS-30512 is implemented in I2T100 technology, enabling both high-voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage requirements. The AMIS-30512 is ideally suited for general-purpose stepper motor applications in the automotive, industrial, medical, and marine environment.
Key Features
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PIN ASSIGNMENT
DO VDD GND DI CLK NXT DIR ERR SLA CPN CPP VCP TSTO POR/WD VBB MOTXP GND MOTXN MOTYN GND MOTYP VBB CS CLR
AMIS30512
* Dual H-Bridge for 2-phase Stepper Motors * Programmable Peak-current up to 800 mA Using a 5-bit Current * * * * * * * * * * * * * *
(Top View)
DAC On-chip Current Translator SPI Interface Speed and Load Angle Output Seven Step Modes from Full-step up to 32 Micro-steps Fully Integrated Current-sense PWM Current Control with Automatic Selection of Fast and Slow Decay Low EMC PWM with Selectable Voltage Slopes Active Fly-back Diodes Full Output Protection and Diagnosis Thermal Warning and Shutdown Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs Integrated 5 V Regulator to Supply External Microcontroller Integrated Reset Function to Reset External Microcontroller Integrated Watchdog Function
ORDERING INFORMATION
Device AMIS30512 Package SOIC 24 Shipping Tape & Reel
(c) Semiconductor Components Industries, LLC, 2008
September, 2008 - Rev. 1
1
Publication Order Number: AMIS-30512/D
AMIS-30512
Table of Contents Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin List and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VDD CLK Timebase Vreg POR CS DI DO NXT DIR SLA POR/WD CLR ERR TST0 Band- gap Temp. Sense Logic & Registers Load Angle SPI OTP
CPN CPP VCP Chargepump EMC T R A N S L A T O R
VBB
I-sense
P W M
MOTXP
MOTXN
EMC
P W M
MOTYP
I-sense AMIS30512
MOTYN
GND
Figure 1. Block Diagram
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Table 1. Pin List and Descriptions
Name DO VDD GND DI CLK NXT DIR ERR SLA CPN CPP VCP CLR CS VBB MOTYP GND MOTYN MOTXN GND MOTXP VBB POR/WD TST0 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SPI data output (open drain) Logic Supply Input (needs external decoupling capacitor) Ground SPI data in SPI clock input Next micro-step input Direction input Error Output (open drain) Speed Load Angle Output Negative connection of charge pump capacitor Positive connection of charge pump capacitor Charge-pump filter-capacitor "Clear" = Chip Reset input SPI chip select input High Voltage Supply Input Negative end of phase Y coil output Ground Positive end of phase Y coil output Positive end of phase X coil output Ground Negative end of phase X coil output High Voltage Supply Input Power-on-reset (POR) and watchdog reset output (open drain) Test pin input (to be tied to ground in normal operation) Description
Table 2. Absolute Maximum Ratings
Symbol VBB Tstrg Tamb VESD Parameter Analog DC supply voltage (Note 1) Storage temperature Ambient temperature under bias Electrostatic discharges on component level (Note 2) Min. -0.3 -55 -50 -2 Max. +40 +160 +150 +2 Units V C C kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s. 2. Human body model (100 pF via 1.5 kW, according to JEDEC EIA-JESD22-A114-B).
Table 3. Recommended Operating Conditions
Symbol VBB Ta Ta Tj NOTE: Analog DC supply Ambient temperature VBB +18 Ambient temperature VBB +30 Junction temperature Parameter Min. +6 -40 -40 Max. +30 +125 +85 +160 Units V C C C
Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability.
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Table 4. DC Parameters (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified. Convention: currents flowing in the circuit are defined as positive.) Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit
SUPPLY INPUTS VBB IBB VDD ILOAD IDDLIM ILOAD_PD VDDH VDDL MOTORDRIVER IMDmax,Peak IMDabs IMDrel ISET_TC Max current through motor coil in normal operation Absolute error on coil current Error on current ratio Icoilx / Icoily Temperature coefficient of coil current set-level, CUR[4:0] = 0 ..31 On-resistance high-side driver, CUR[4:0] = 0...31; Range 0...3 On-resistance low-side driver, CUR[4:0] = 23...31; Range 3 On-resistance low-side driver, CUR[4:0] = 16...22; Range 2 On-resistance low-side driver, CUR[4:0] = 9...15; Range 1 On-resistance low-side driver, CUR[4:0] = 0...8; Range 0 Pull-down current -40C Tj 160C Tj < Tstd -10 -7 -240 800 10 7 mA % % ppm/C VDD VDD VBB Nominal operating supply range Total current consumption Regulated output voltage Max. output current 6 V < VBB < 8 V 8 V < VBB < 30 V Current limitation Output current in power down VDD shorted to ground 1 Unloaded outputs 4.75 20 50 200 5 6 30 8 5.25 V mA V mA mA mA mA
POWER-ON-RESET (POR) Internal POR comparator threshold Internal POR comparator threshold VDD rising VDD falling 4.0 4.25 3.68 4.4 V V
RHS MOTXP MOTXN MOTYP MOTYN
Vbb = 12 V, Tj = 27C Vbb = 12 V, Tj = 160C Vbb = 12 V, Tj = 27C Vbb = 12 V, Tj = 160C Vbb = 12 V, Tj = 27C Vbb = 12 V, Tj = 160C Vbb = 12 V, Tj = 27C Vbb = 12 V, Tj = 160C Vbb = 12 V, Tj = 27C Vbb = 12 V, Tj = 160C HiZ mode
0.45 0.94 0.45 0.94 0.90 1.9 1.8 3.8 3.6 7.5 0.5
0.56 1.25 0.56 1.25 1.2 2.5 2.3 5.0 4.5 10
W W W W W W W W W W mA
RLS3 RLS2 RLS1 RLS0 IMpd
LOGIC INPUTS Ileak VIL VIH Rpd_CLR Rpd_TST Input leakage (Note 3) DI, CLK NXT, DIR Logic low threshold CLR, CSB Logic high threshold CLR TST0 Internal pull-down resistor Internal pull-down resistor Tj = 160C 0 2.20 120 3 1 0.65 VDD 300 9 mA V V kW kW
3. Not valid for pins with internal pull-down resistor 4. No more than 100 cumulated hours in life time above Ttw 5. Thermal shutdown and low temperature warning are derived from thermal warning.
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Table 4. DC Parameters (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified. Convention: currents flowing in the circuit are defined as positive.) Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit
LOGICAL OUTPUTS VOL DO, ERRB, POR/WD Logic Low level open drain IOL = 5 mA 0.5 V
THERMAL WARNING AND SHUTDOWN Ttw Ttsd (Notes 4,5) CHARGE PUMP Vcp Cbuffer Cpump Vout Voff Rout Cload Gsla CPP CPN VCP Output voltage 6 V < VBB < 15 V 15 V < VBB < 30 V External buffer capacitor External pump capacitor VBB+11 180 180 2 * VBB - 2.5 VBB+12.8 220 220 VBB+15 470 470 V V nF nF Thermal warning Thermal shutdown 138 145 Ttw + 20 152 C C
SPEED AND LOAD ANGLE OUTPUT SLA Output voltage range Output offset the SLA pin Output resistance SLA pin Load capacitance SLA pin Gain of SLA pin = VBEMF / VCOIL SLAG=0 SLAG=1 0,5 0,25 0.2 V < Vsla < Vdd - 0,2 V 0.5 -25 4.5 25 1 50 V mV kW pF
3. Not valid for pins with internal pull-down resistor 4. No more than 100 cumulated hours in life time above Ttw 5. Thermal shutdown and low temperature warning are derived from thermal warning.
Table 5. AC Parameters (The AC parameters are given for VBB and temperature in their operating ranges.)
Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit INTERNAL OSCILLATOR fosc MOTORDRIVER fPWM fJF fDF TS_RISE MOTXP MOTXN MOTYP MOTYN PWM frequency Double PWM frequency PWM Jitter frequency PWM Jitter depth turn-on voltage slope, 10% to 90% IMD = 800 mA EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 TS_FALL turn-off voltage slope, 90% to 10% IMD = 800 mA EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 tOC Open coil detection time = 0 = 1 Not measured in production 20.8 41.6 22.8 45.6 50 7 150 100 50 25 150 100 50 25 200 24.8 49.6 kHz kHz Hz % fPWM V/ms V/ms V/ms V/ms V/ms V/ms V/ms V/ms ms Frequency of internal oscillator 3.6 4 4.4 MHz
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Table 5. AC Parameters (The AC parameters are given for VBB and temperature in their operating ranges.)
Symbol Pin(s) Parameter Remark/Test Conditions Min. Typ. Max. Unit DIGITAL OUTPUTS tH2L DO ERRB Output fall-time from VinH to VinL Capacitive load 50 pF 50 ns
CHARGE PUMP fCP tCPU CPN CPP MOTxx Charge pump frequency Start-up time of charge pump For typ. value Cbuffer and Cpump 250 2 kHz ms
CLR FUNCTION tCLR tNXT_HI tNXT_LO tDIR_SET tDIR_HOLD POWER-UP tPU tPD tPOR tRF WATCHDOG tWDTO tWDPR tWDRD POR/ WD Watchdog time out interval Prohibited watchdog acknowledge delay Watchdog reset delay See Figure 3 See Figure 3 32 2 1 512 ms ms ms POR/ WD Power-up time Power-down time Reset duration Reset filter time VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF. See Figure 3 VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF. . See Figure 3 See Figure 3 See Figure 3 100 1 110 110 ms ms ms ms CLR Hard reset duration time 20 90 ms
NXT FUNCTION NXT NXT minimum, high pulse width NXT minimum, low pulse width NXT hold time, following change of DIR NXT hold time, before change of DIR See Figure 2 See Figure 2 See Figure 2 See Figure 2 2 2 0.5 0.5 ms ms ms ms
tNXT_HI
tNXT_LO
NXT tDIR_SET
0,5 VCC tDIR_HOLD
DIR
VALID
Figure 2. NXT-input Timing Diagram
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IIIIIIIIII IIIIIIIIII IIIIIIIIII
II II II
AMIS-30512
VBB
t VDD VDDH VDDL t < tRF tPU tPD
POR/WD pin tPOR tRF
Figure 3. Power-on-Reset Timing Diagram
VBB
t VDD VDDH t tPOR tPU
POR/WD pin tDSPI tWDRD tPOR
Enable WD > tWDPR and < tWDTO Acknowledge WD t tWDTO = tWDPR or = tWDTO
WD timer
t
Figure 4. Watchdog Timing Diagram
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Table 6. SPI Timing Parameters
Symbol tCLK tCLK_HIGH tCLK_LOW tSET_DI tHOLD_DI tCSB_HIGH tSET_CSB tSET_CLK SPI clock period SPI clock high time SPI clock low time DI set up time, valid data before rising edge of CLK DI hold time, hold data after rising edge of CLK CSB high time CSB set up time, CSB low before rising edge of CLK CLK set up time, CLK low before rising edge of CSB Parameter Min. 1 100 100 50 50 2.5 100 100 Typ. Max. Unit ms ns ns ns ns ms ns ns
CS tSET_CSB
0,2 VCC tCLK 0,8 VCC tSET_CLK
0,2 VCC
CLK
0,2 VCC tCLK_HI tSET_DI tHOLD_DI tCLK_LO
0,2 VCC
DI
0,8 VCC VALID
Figure 5. SPI Timing
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IIIIIIIIII IIIIIIIIII IIIIIIIIII
II II II
AMIS-30512
100 nF C5 100 nF R2 R3 R4 C4 100 nF C2 VDD 100 nF C3 VBB VBB VCP POR/WD DIR NXT DO DI mC CLK CS CLR ERR SLA C8 R1 GND MOTYP MOTYN AMIS-30512 CPN C7 C1 C6 220 nF 100 mF D1 VBAT
220 nF CPP MOTXP MOTXN M
Figure 6. Typical Application Schematic
Table 7. External Components List and Description
Component C1 C2, C3 C4 C5 C6 C7 C8 R1 R2, R3, R4 D1 6. Low ESR < 1 Ohm. Function VBB buffer capacitor (Note 6) VBB decoupling block capacitor VDD buffer capacitor VDD buffer capacitor Charge pump buffer capacitor Charge pump pumping capacitor Low pass filter SLA Low pass filter SLA Pull up resistor Optional reverse protection diode Typ. Value 100 100 220 100 220 220 1 5.6 4.7 e.g. 1N4003 Tolerance -20 +80% -20 +80% 20% 20% 20% 20% 20% 1% 1% Unit mF nF nF nF nF nF nF kW kW
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Functional Description
H-Bridge Drivers
A full H-bridge is integrated for each of the two stator windings. Each H-bridge consists of two low-side and two high-side N-type MOSFET switches. Writing logic `0' in bit disables all drivers (high-impedance). Writing logic `1' in this bit enables both bridges and current can flow in the motor stator windings. In order to avoid large currents through the H-bridge switches, it is guaranteed that the top- and bottom-switches of the same half-bridge are never conductive simultaneously (interlock delay). A two-stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched-off. In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (Table 25: SPI Control Parameter Overview EMC[1:0]). The power transistors are equipped with so-called "active diodes": when a current is forced through the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain-bulk diode.
Depending on the desired current range and the micro-step position at hand, the Rdson of the low-side transistors will be adapted such that excellent current-sense accuracy is maintained. The Rdson of the high-side transistors remain unchanged, see Table 4: DC Parameters for more details.
PWM Current Control
A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H-bridge switches. The switching points of the PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter can be added (Table 14: SPI Control Register 1). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor-speed or load-conditions of the motor have no effect. There are no external components required to adjust the PWM frequency.
Automatic Forward and Slow-Fast Decay
The PWM generation is in steady-state using a combination of forward and slow-decay. The absence of fast-decay in this mode, guarantees the lowest possible current-ripple "by design". For transients to lower current levels, fast-decay is automatically activated to allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation.
Icoil Set value
Actual value t TPWM
0
Forward & Slow Decay Fast Decay & Forward
Forward & Slow Decay
Figure 7. Forward and Slow/Fast Decay PWM
In case the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the requested average current in the coils. This process is completely automatic and requires no additional
parameters for operation. The over-all current-ripple is divided by two if PWM frequency is doubled (Table 14: SPI Control Register 1).
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Icoil Duty Cycle < 50%
Duty Cycle > 50% Actual value
Duty Cycle < 50%
Set value
t TPWM
Figure 8. Automatic Duty Cycle Adaptation
Step Translator
Step Mode
The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL, and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of seven possible stepping modes can be selected through SPI-bits SM[2:0] (Table 26: SPI Control Parameter Overview SM[2:0]) After power-on or hard reset, the coil-current translator is set to the default 1/32 micro-stepping at position `0'. Upon changing the step
mode, the translator jumps to position 0* of the corresponding stepping mode. When remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 9 lists the output current versus the translator position. As shown in Figure 9 the output current-pairs can be projected approximately on a circle in the (Ix,Iy) plane. There is, however, one exception: uncompensated half step. In this step mode the currents are not regulated to a fraction of Imax but are in all intermediate steps regulated at 100 percent. In the (Ix,Iy) plane the current-pairs are projected on a square. Table 8 lists the output current versus the translator position for this case.
Table 8. Square Translator Table for Full Step and Uncompensated Half Step
Stepmode ( SM[2:0] ) 101 MSP[6:0] 000 0000 001 0000 010 0000 011 0000 100 0000 101 0000 110 0000 111 0000 Uncompensated Half-Step 0* 1 2 3 4 5 6 7 110 Full Step - 1 - 2 - 3 - 0* Coil x 0 100 100 100 0 -100 -100 -100 Coil y 100 100 0 -100 -100 -100 0 100 % of Imax
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Table 9. Circular Translator Table
Stepmode ( SM[2:0] ) 000 MSP[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 1/32 `0' 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 001 1/16 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 010 1/8 0* 1 2 3 4 5 6 7 8 9 10 011 1/4 0* 1 2 3 4 5 100 1/2 0* 1 2 Coil x 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 Coil y 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 % of Imax
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Table 9. Circular Translator Table
Stepmode ( SM[2:0] ) 000 MSP[6:0] 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 1/32 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 001 1/16 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 010 1/8 11 12 13 14 15 16 17 18 19 20 21 011 1/4 6 7 8 9 10 100 1/2 3 4 5 Coil x 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 Coil y -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 % of Imax
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Table 9. Circular Translator Table
Stepmode ( SM[2:0] ) 000 MSP[6:0] 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 1/32 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 001 1/16 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 010 1/8 22 23 24 25 26 27 28 29 30 31 011 1/4 11 12 13 14 15 100 1/2 6 7 Coil x -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 Coil y -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 % of Imax
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Iy Iy Iy
Start = 0
Step 1 Step 2 Step 3 Ix
Start = 0
Step 1
Start = 0
Step 1
Step 2 Ix Ix
Step 3 1/4th micro step SM[2:0] = 011 Uncompensated Half Step SM[2:0] = 101
Step 3
Step 2
Full Step SM[2:0] = 110
Figure 9. Translator Table: Circular and Square Direction Translator Position
The direction of rotation is selected by means of following combination of the DIR input pin and the SPI-controlled direction bit . (Table 14: SPI Control Register 1)
NXT Input
Changes on the NXT input will move the motor current one step up/down in the translator table. Depending on the NXT-polarity bit (Table 14: SPI Control Register 1), the next step is initiated either on the rising edge or the falling edge of the NXT input.
The translator position can be read in Table 30: SPI Status Register 3. This is a 7-bit number equivalent to the 1/32th micro-step from Table 9: Circular Translator Table. The translator position is updated immediately following a NXT trigger.
NXT
Update Translator Position
Update Translator Position
Figure 10. Translator Position Timing Diagram Synchronization of Step Mode and NXT Input
When step mode is re-programmed to another resolution (Table 13: SPI Control Register 0), then this is put in effect immediately upon the first arriving "NXT" input. If the micro-stepping resolution is increased (see Figure 11 left hand side) then the coil currents will be regulated to the nearest micro-step, according to the fixed grid of the increased resolution. If however the micro-stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro-step translator table. If the step resolution is decreased at a translator table position that is shared both by the old and new resolution
setting, then the offset is zero and micro-stepping proceeds according to the translator table. If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro-stepping is proceeds according to the translator table. If the translator position is not shared both by the old and new resolution setting, then the micro-stepping proceeds with an offset relative to the translator table (See Figure 11 right hand side).
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Change from lower to higher resolution Iy endpos DIR NXT4 NXT2 NXT3 Iy NXT1 DIR startpos Change from higher to lower resolution Iy endpos DIR NXT2 Ix Ix Iy NXT1 startpos DIR
Ix
Ix
NXT3
Halfstep
1/4th step
1/8th step
Halfstep
Left: Change from lower to higher resolution. The left-hand side depicts the ending half-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the micro-step position. Right: Change from higher to lower resolution. The left-hand side depicts the ending micro-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the half-step position.
Figure 11. NXT-Step Mode Synchronization
NOTE: It is advised to reduce the micro-stepping resolution only at micro-step positions that overlap with desired micro-step positions of the new resolution.
Programmable Peak-Current
The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter "CUR[4:0]" (Table 13: SPI Control Register 0). Whenever this parameter is changed, the coil-currents will
Table 10. Programmable Peak Current CUR[4:0]
Current Range 0 CUR[4:0] Index 0 1 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 NOTE: Current (mA) 15 30 45 50 55 61 67 74 82 91 100 110 122 135 149 164
be updated immediately at the next PWM period. The impedance of the bottom drivers is adapted with the current range: See Table 4: DC Parameters.
Current Range 2
CUR[4:0] Index 16 17 18 19 20 21 22
Current (mA) 181 200 221 244 269 297 328 362 400 441 487 538 594 656 724 800
3
23 24 25 26 27 28 29 30 31
Changing the current over different current ranges might lead to false over current triggering.
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AMIS-30512
Speed and Load Angle Output
The SLA-pin provides an output voltage that indicates the level of the Back-e.m.f. voltage of the motor. This Back-e.m.f. voltage is sampled during every so-called "coil
I COIL
current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding in total four zero-current observation points per electrical period.
V BEMF
t
ZOOM Previous Micro-step ICOIL Coil Current Zero Crossing Current Decay Zero Current t VCOIL VBB Voltage Transient Next Micro-step
VBEMF t
Figure 12. Principle of Bemf Measurement
Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit (see "SLA-transparency" in Table 15: SPI Control Register 2). The SLA pin shows in "transparent mode" full visibility of the voltage transient behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If the bit "SLAT" is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin. Because the transient behavior
of the coil voltage is not visible any more, this mode generates smoother Back e.m.f. input for post-processing, e.g. by software. In order to bring the sampled Back e.m.f. to a descent output level (0 to 5 V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through an SPI bit . (Table 15: SPI Control Register 2) The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals that define together with SLAT the sampling and hold moments of the coil voltage.
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AMIS-30512
VCOIL
div2 div4
Ssh Csh
Sh
buf
SLA-pin
Ch
Icoil = 0 PWMsh
SLAT NOT (Icoil = 0)
PWMsh Icoil = 0 SLAT
VCOIL
t SLA-pin
last sample is retained
VBEMF
previous output is kept at SLA pin
retain last sample
t
SLAT = 1 SLA-pin is "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated "real-time".
SLAT = 0 SLA-pin is not "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated when leaving current-less state.
Figure 13. Timing Diagram of SLA-pin
Warning, Error Detection and Diagnostics Feedback
Thermal Warning and Shutdown
When junction temperature rises above TTW, the thermal warning bit is set (Table 27: SPI Status Register 0). If junction temperature increases above thermal shutdown level, then the circuit goes in "thermal shutdown" mode, bit is set and all driver transistors are disabled (high impedance) (Table 29: SPI Status Register 2). The conditions to reset flag is to be at a temperature lower than TTW and to clear the flag by reading it using any SPI read command.
Over-Current Detection
condition is latched and the microcontroller needs to clean the status bits to reactivate the drivers.
NOTE: Successive reading the SPI Status Registers 1 and 2 in case of a short circuit condition, may lead to damage to the drivers. Changing the current over different current ranges might lead to false over current triggering.
Open Coil Detection
The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. Each driver transistor has an individual detection bit in the Table 28: SPI Status Register 1 and Table 29: SPI Status Register 2 ( and ). Error
Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle is detected for longer than tOC = 200 ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI status register is set ( or ). (Table 27: SPI Status Register 0).
Charge Pump Failure
The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If the supply voltage is too low or external components are
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AMIS-30512
not properly connected to guarantee sufficient low Rdson of the drivers, then the bit is set in Table 27: SPI Status Register 0. Also after power-on-reset the charge pump voltage will need the time tCPU to exceed the required threshold. During that time will be set to "1".
Error Output
chip, some low-voltage analog blocks and external circuitry. The voltage is derived from an internal bandgap reference. To calculate the available drive-current for external circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See DC parameters.
Power-On Reset (POR) Function
This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = OR OR OR OR OR
Logic Supply Regulator
AMIS-30512 has an on-chip 5 V low-drop regulator with external decoupling capacitor to supply the digital part of the
VBB
The open drain output pin POR/WD provides an "active low" reset for external purposes. At power-up of AMIS-30512, this pin will be kept low for some time to reset for example an external microcontroller. A small analog filter avoids resetting due to spikes or noise on the VDD supply.
t VDD VDDH VDDL < tRF t tPU tPD
POR/WD pin tPOR tRF
Figure 14. Power-on-Reset Timing Diagram Watchdog Function
The watchdog function is enabled/disabled through bit (Table 12: SPI Control Register WR). Once this bit has been set to "1" (watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. In case the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then
a reset of the microcontroller will occur through POR/WD pin. In addition, a warm/cold boot bit is available in SPI Status Register 0 for further processing when the external microcontroller is alive again. The watchdog reset delay tWDRD is determined by an internal delay of 0,5 ms added to an external delay formed by the pull up resistance and the capacitive load on the POR/WD pin.
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AMIS-30512
VBB
t VDD VDDH t tPOR POR/WD pin tDSPI tWDRD = tWDPR or = tWDTO > tWDPR or < tWDTO Acknowledge WD t tWDTO tPOR tPU
Enable WD
WD timer
t
Figure 15. Watchdog Timing Diagram
NOTE: tDSPI is the time needed by the external microcontroller to shift-in the bit after a power-up.
The duration of the watchdog timeout interval is programmable through the WDT [3:0] bits (Table 12: SPI Control Register WR). The timing is given in Table 11.
Table 11. Watchdog Timeout Interval as Function of WDT[3.0]
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WDT[3:0] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tWDTO (ms) 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30512, the input CLR needs to be pulled to logic 1 during minimum time given by TCLR. (Table 5: AC Parameters) This reset function clears all internal registers without the need of a power-cycle. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again.
Sleep Mode
The bit in Table 15: SPI Control Register 2 is provided to enter a so-called "sleep mode". This mode allows reduction of current-consumption when the motor is not in operation. The effect of sleep mode is as follows: * The drivers are put in HiZ * All analog circuits are disabled and in low-power mode * All internal registers are maintaining their logic content * Pulses on NXT and DIR inputs are ignored * SPI communication remains possible (slight current increase during SPI communication) * Reset of chip is possible through CLR pin * Oscillator and digital clocks are silent, except during SPI communication Normal operation is resumed after writing logic `0' to bit . A start-up time tCPU is needed for the charge pump to stabilize. After this time, NXT commands can be issued.
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AMIS-30512
SPI Interface The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS-30512. The implemented SPI block is designed to interface directly with numerous micro-controllers from several manufacturers. AMIS-30512 acts always as a Slave and can't initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI).
# CLK cycle CS 1 2 3 4
DO signal is the output from the Slave (AMIS-30512), and DI signal is the output from the Master. A chip select line (CSB) allows individual selection of a Slave SPI device in a multiple-slave system. The CSB line is active low. If AMIS-30512 is not selected, DO is pulled up with the external pull up resistor. Since AMIS-30512 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave.
5 6 7 8
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
Figure 16. Timing Diagram of a SPI Transfer
NOTE:
At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS-30512 system clock when CSB = High
Transfer Packet:
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
BYTE 1 Command and SPI Register Address MSB LSB MSB D7 D6 D5 D4 D3 D2 D1 BYTE 2 Data LSB D0
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Command SPI Register Address
Figure 17. SPI Transfer Packet
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IIIII IIIII IIII IIII
AMIS-30512
Byte 1 contains the Command and the SPI Register Address and indicates to AMIS-30512 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS-30512 in a READ operation. 2 command types can be distinguished in the communication between master and AMIS-30512: * READ from SPI Register with address ADDR[4:0]: CMD2 = "0" * WRITE to SPI Register with address ADDR[4:0]: CMD2 = "1"
READ Operation
If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the corresponding internal SPI register. In the next 8-bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or is dummy data.
Registers are updated with the internal status at the rising edge of the internal AMIS-30512 clock when CS = 1
CS
COMMAND DI DATA from previous command or NOT VALID after POR or RESET DATA DO OLD DATA or NOT VALID DATA DATA from ADDR1 READ DATA from ADDR1 COMMAND or DUMMY
Figure 18. Single READ operation where DATA from SPI register with Address 1 is read by the Master
All 4 Status Registers (see SPI Status Registers) contain 7 data bits and a parity check bit. The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals "1". If the number of logical ones in D[6:0] is even then the parity bit D7 equals "0". This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. Also the Control Registers (see SPI Control Registers) can be read out following the same routine. Control Registers don't have a parity check. The CSB line is active low and may remain low between successive READ commands as illustrated in Figure 18. There is however one exception. In case an error condition is latched in one of Status Registers (see SPI Registers) the ERRB pin is activated. (See Error Output). This signal flags a problem to the external microcontroller. By reading the Status Registers information about the root cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status Registers and ERRB pin are only updated by the internal system clock when the CSB line is high, the Master should force CSB high
immediately after the READ operation. For the same reason it is recommended to keep the CSB line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CSB goes from low to high! AMIS-30512 responds on every incoming byte by shifting out via DO the data stored in the last received address. It is important that the writing action (command - address and data) to the Control Register is exactly 16 bits long. If more or less bits are transmitted the complete transfer packet is ignored. A WRITE command executed for a read-only register (e.g. Status Registers) will not affect the addressed register and the device operation. Because after a power-on-reset the initial address is unknown the data shifted out via DO is not valid.
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AMIS-30512
The NEW DATA is written into the corresponding internal register at the rising edge of CS CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR3 DATA OLD DATA or NOT VALID DATA NEW DATA for ADDR3 DATA OLD DATA from ADDR3
Figure 19. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3 Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE operations are combined. In Figure 17 the Master first reads the status from Register at ADDR4 and at ADDR5 followed
Registers are updated with the internal status at the rising edge of the internal AMIS-30512 clock when CS = 1 CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO READ DATA from ADDR4 DATA OLD DATA or NOT VALID
by writing a control byte in Control Register at ADDR2. Note that during the write command (in Figure 3) the old data of the pointed register is returned at the moment the new data is shifted in:
The NEW DATA is written into the corresponding internal register at the rising edge of CS
COMMAND READ DATA from ADDR5 DATA DATA from ADDR4
COMMAND WRITE DATA to ADDR2 DATA DATA from ADDR5
DATA NEW DATA for ADDR2 DATA OLD DATA from ADDR2
Figure 20. 2 Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read back command in order to verify the data correctly written as illustrated in Figure 18. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is
Registers are updated with the internal status at the rising edge of CS CS COMMAND DI Data from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR2 DATA OLD DATA or NOT VALID DATA NEW DATA for ADDR2 DATA OLD DATA from ADDR2
transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CSB line is high, the first read out byte might represent old status information.
Registers are updated with the internal status at the rising edge of the internal AMIS-30512 clock when CS = 1
COMMAND READ DATA from ADDR2 DATA OLD DATA from ADDR2 COMMAND or DUMMY DATA NEW DATA from ADDR2
Figure 21. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Confirm a Correct WRITE Operation
NOTE: The internal data-out shift buffer of AMIS-30512 is updated with the content of the selected SPI register only at the last (every eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
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AMIS-30512
SPI Control Registers
All SPI control registers have Read/Write access and default to "0" after power-on or hard reset.
Table 12. SPI Control Register WR
Control Register (WR) Structure Address Content Access 00h Reset Data Bit 7 R/W 0 WDEN Bit 6 R/W 0 Bit 5 R/W 0 WDT[3:0] Bit 4 R/W 0 Bit 3 R/W 0 Bit 2 R/W 0 - Bit 1 R/W 0 - Bit 0 R/W 0 -
Where: R/W Reset: WDEN: WDT[3:0]:
Read and Write access Status after power-On or hard reset Watchdog enable. Writing "1" to this bit will activate the watchdog timer (if not enabled yet) or will clear this timer (if already enabled). Writing "0" to this bit will clear WD bit (SPI Status Register 0). Watchdog timeout interval
Table 13. SPI Control Register 0
Control Register 0 (CR0) Structure Address Content Access 01h Reset Data Bit 7 R/W 0 Bit 6 R/W 0 SM[2:0] Bit 5 R/W 0 Bit 4 R/W 0 Bit 3 R/W 0 Bit 2 R/W 0 CUR[4:0] Bit 1 R/W 0 Bit 0 R/W 0
Where: R/W Reset: SM[2:0]: CUR[4:0]:
Read and Write access Status after power-On or hard reset Step mode Current amplitude
Table 14. SPI Control Register 1
Control Register 1 (CR1) Structure Address Content Access 02h Reset Data Bit 7 R/W 0 DIRCTRL Bit 6 R/W 0 NXTP Bit 5 R/W 0 - Bit 4 R/W 0 - Bit 3 R/W 0 PWMF Bit 2 R/W 0 PWMJ Bit 1 R/W 0 EMC[1:0] Bit 0 R/W 0
Where: R/W Reset: DIRCTRL NXTP PWMF PWMJ EMC[1:0]
Read and Write access Status after power-on or hard reset Direction control NEXT polarity PWM frequency PWM jitter EMC slope control
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Table 15. SPI Control Register 2
Control Register 2 (CR2) Structure Address Content Access 03h Reset Data Bit 7 R/W 0 MOTEN Bit 6 R/W 0 SLP Bit 5 R/W 0 SLAG Bit 4 R/W 0 SLAT Bit 3 R/W 0 - Bit 2 R/W 0 - Bit 1 R/W 0 - Bit 0 R/W 0 -
Where: R/W Reset: MOTEN
Symbol SLAT
Read and Write access Status after power-On or hard reset Motor enable
Description Speed Load Angle Transparency bit
SLP SLAG SLAT
Status = 0 = 1
Sleep Speed load angle gain Speed load angle transparency
Behaviour SLA is transparent SLA is NOT transparent
Table 16. SPI Control Parameter Overview SLAT
Table 17. SPI Control Parameter Overview SLAG
Symbol SLAG Description Speed Load Angle Gain setting Status = 0 = 1 Gain = 0.5 Gain = 0.25 Value
Table 18. SPI Control Parameter Overview PWMF
Symbol PWMF Description Enables doubling of the PWM frequency Status = 0 = 1 fPWM = 22.8 kHz fPWM = 45.6 kHz Behaviour Jitter disabled Jitter enabled Value
Table 19. SPI Control Parameter Overview PWMJ
Symbol PWMJ Description Enables jittery PWM Status = 0 = 1
Table 20. SPI Control Parameter Overview SLP
Symbol SLP Description Enables sleep mode Status = 0 = 1 Active mode Sleep mode Behaviour
Table 21. SPI Control Parameter Overview MOTEN
Symbol MOTEN Description Activates the motor driver outputs Status = 0 = 1 Drivers disabled Drivers enabled Value
Table 22. SPI Control Parameter Overview DIRCTRL
Symbol DIRCTRL Description Controls the direction of rotation (in combination with logic level on input DIR) = 0 = 1 Status = 0 = 1 = 0 = 1 Value CW motion CCW motion CCW motion CW motion
Table 23. SPI Control Parameter Overview NXTP
Symbol NXTP Description Selects if NXT triggers on rising or falling edge Status = 0 = 1 Value Trigger on rising edge Trigger on falling edge
CUR[4:0]
Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
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Table 24. SPI Control Parameter Overview CUR[4:0]
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CUR[4:0] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Current (mA) 15 30 45 50 55 61 67 74 82 91 100 110 122 135 149 164 Index 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CUR[4:0] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Current (mA) 181 200 221 244 269 297 328 362 400 441 487 538 594 656 724 800
EMC[1:0]
Adjusts the dV/dt of the PWM voltage slopes on the motor pins.
Table 25. SPI Control Parameter Overview EMC[1:0]
Index 0 1 2 3 EMC[1:0] 0 0 1 1 0 1 0 1 Slope (V/ms) 150 100 50 25 Remark Turn-on and turn-off voltage slope 10% to 90% " " "
SM[2:0]
Selects the micro-stepping mode.
Table 26. SPI Control Parameter Overview SM[2:0]
Index 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 SM[2:0] 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Step Mode 1/32 1/16 1/8 1/4 1/2 1/2 Full N/A Remark Micro-step Micro-step Micro-step Micro-step Uncompensated half-step Compensated half-step Full step For future use
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SPI Status Register Description
All four SPI status registers have Read Access and are default to "0" after power-on or hard reset.
Table 27. Status Register 0 (SR0)
Structure Address Content Access 04h Reset Data Bit 7 R 0 PAR Bit 6 R 0 TW Bit 5 R 0 CPfail Bit 4 R 0 - Bit 3 R 0 OPENX Bit 2 R 0 OPENY Bit 1 R 0 - Bit 0 R 0 -
Where: R Reset PAR TW Cpfail OPENX OPENY Remark:
Read only mode access Status after power-on or hard reset Parity check Thermal warning Charge pump failure Open Coil X detected Open Coil Y detected Data is not latched
Table 28. Status Register 1 (SR1)
Structure Address Content Access 05h Reset Data Bit 7 R 0 PAR Bit 6 R 0 OVCXPT Bit 5 R 0 OVCXPB Bit 4 R 0 OVCXNT Bit 3 R 0 OVCXNB Bit 2 R 0 - Bit 1 R 0 - Bit 0 R 0 -
Where: R Reset PAR OVXPT OVXPB OVXNT OVXNB Remark:
Read only mode access Status after power-on or hard reset Parity check Over-current detected on X H-bridge: MOTXP terminal, top transistor Over-current detected on X H-bridge: MOTXP terminal, bottom transistor Over-current detected on X H-bridge: MOTXN terminal, top transistor Over-current detected on X H-bridge: MOTXN terminal, bottom transistor Data is latched
Table 29. SPI Status Register 2 (SR2)
Structure Address Content Access 06h Reset Data Bit 7 R 0 PAR Bit 6 R 0 OVCYPT Bit 5 R 0 OVCYPB Bit 4 R 0 OVCYYNT Bit 3 R 0 OVCYNB Bit 2 R 0 TSD Bit 1 R 0 - Bit 0 R 0 -
Where: R Reset PAR OVCYPT OVCYPB OVCYNT OVCYNB TSD Remark:
Read only mode access Status after power-on or hard reset Parity check Over-current detected on Y H-bridge: MOTYP terminal, top transistor Over-current detected on Y H-bridge: MOTYP terminal, bottom transistor Over-current detected on Y H-bridge: MOTYN terminal, top transistor Over-current detected on Y H-bridge: MOTYN terminal, bottom transistor Thermal shutdown Data is latched
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Table 30. SPI Status Register 3 (SR3)
Structure Address Access 07h Reset Data Content Bit 7 R 0 PAR Bit 6 R 0 Bit 5 R 0 Bit 4 R 0 MSP[6:0] Bit 3 R 0 Bit 2 R 0 Bit 1 R 0 Bit 0 R 0
Where: R Reset PAR MSP[6:0] Remark:
Read only mode access Status after power-on or hard reset Parity check Translator micro-step position Data is not latched
Table 31. SPI Status Flags Overview
Flag Charge pump failure Mnemonic CPFail Length (bit) 1 Related SPI Register Status Register 0 Comment `0' = no failure `1' = failure: indicates that the charge pump does not reach the required voltage level. Translator micro-step position `1' = Open coil detected `1' = Open coil detected `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YP-terminal Reset State `0'
Micro-step position OPEN Coil X OPEN Coil Y OVer Current on X H-bridge; MOTXN terminal; Bottom tran. OVer Current on X H-bridge; MOTXN terminal; Top tran. OVer Current on X H-bridge; MOTXP terminal; Bottom tran. OVer Current on X H-bridge; MOTXP terminal; Top tran. OVer Current on Y H-bridge; MOTYN terminal; Bottom tran. OVer Current on Y H-bridge; MOTYN terminal; Top tran. OVer Current on Y H-bridge; MOTYP terminal; Bottom tran. OVer Current on Y H-bridge; MOTYP terminal; Top tran. Thermal shutdown Thermal warning Watchdog event
MSP [6:0] OPENX OPENY OVCXNB
7 1 1 1
Status Register 3 Status Register 0 Status Register 0 Status Register 1
`0000000' `0' `0' `0'
OVCXNT
1
Status Register 1
`0'
OVCXPB
1
Status Register 1
`0'
OVCXPT
1
Status Register 1
`0'
OVCYNB
1
Status Register 2
`0'
OVCYNT
1
Status Register 2
`0'
OVCYPB
1
Status Register 2
`0'
OVCYPT
1
Status Register 2
`0'
TSD TW WD
1 1 1
Status Register 2 Status Register 0 Status Register 0 `1' = watchdog reset after time-out
`0' `0' `0'
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AMIS-30512
Soldering
Introduction to Soldering Surface Mount Packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards (PCB) with high population densities. In these situations re-flow soldering is often used.
Re-flow Soldering
* Use a double-wave soldering method comprising a
Re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the PCB by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for re-flowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on the heating method. Typical re-flow peak temperatures range from 215 to 260C. The top-surface temperature of the packages should preferably be kept below 230C.
Wave Soldering
turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): 1. Larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the PCB; 2. Smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the PCB. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the PCB. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is four seconds at 250C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Manual Soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or PCBs with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems, the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Table 32. Soldering Process
Fix the component by first soldering two diagonallyopposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300C. When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320C.
Soldering Method Package BGA, SQFP HLQFP, HSQFP, HSOP, HTSSOP, SMS PLCC (Note 9) , SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Wave Not suitable Not suitable (Note 8) Suitable Not recommended (Notes 9 and 10) Not recommended (Note 11) Re-flow (Note 7) Suitable Suitable Suitable Suitable Suitable
7. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods." 8. These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 9. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 10. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 11. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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AMIS-30512
PACKAGE DIMENSIONS
24 LEAD SOIC CASE 751AW ISSUE O
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AMIS-30512/D

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